1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having numerous trench capacitors and switching transistors. This invention also relates to a method for producing the semiconductor memory device.
2. Description of the prior Art
FIG. 4 shows the memory cell structure of a conventional semiconductor memory device such as a dynamic random access memory (DRAM).
This conventional semiconductor memory device includes a plurality of memory cells, each of which has a trench capacitor 40 formed in a P-type silicon substrate 32, and a switching transistor 41 connected to the trench capacitor 40.
The trench capacitor 40 has an N-type impurity diffused layer 33 which is formed on the sides of a trench 42 provided in the silicon substrate 32, a capacitive oxide film 34 which is formed on the trench 42, and a cell plate 31 which is embedded in the trench 42.
The N-type impurity diffused layer 33 is connected to the source region 37 of the switching transistor 41. The drain region 38 of the switching transistor 41 is connected to a bit line 36. The bit line 36 is formed on an insulating film 39a which is deposited on the silicon substrate 32 so as to cover a gate electrode 35.
A plurality of other switching transistors 41 (not shown) are also connected to the same bit line 36.
An insulating film 39b is deposited over the insulating film 39a so as to cover the bit line 36.
The electrical connection between the source region 37 and the drain region 38 is opened and closed by controlling the potential level at the gate electrode 35 of the switching transistor 41.
Data is written into the capacitor 40, when the switching transistor 41 is in the on state, by causing a charge to flow from the bit line 36 into the N-type impurity diffused layer 33 of the capacitor 40 by way of the drain region 38, the surface of the silicon substrate 32 below the gate electrode 35, and the source region 37.
When the switching transistor 41 is in the off state, the charge remains held in the capacitor 40.
When the switching transistor 41 is turned to the on state, the charge stored in the N-type impurity diffused layer 33 of the capacitor 40 is caused to flow into the bit line 36 by way of the source region 37, the surface of the silicon substrate 32 below the gate electrode 35, and the drain region 38, thus reading the data stored in the capacitor 40.
In the conventional semiconductor memory device, the source region 37 and drain region 38 of the switching transistor 41 are formed in a self-aligning manner by implanting ions into the silicon substrate 32 with the gate electrode 35 as a mask (see, for example, M. Sahamoto et al., "Buried Storage Electrode (BSE) Cell For Megabit DRAMS", IEDM Dig. of Tech Papers (1985) P. 710).
The above-described technique, however, has the following problems.
For the purpose of achieving a higher degree of integration, it is required to reduce the size of the switching transistor 41 in a lateral direction. To reduce the size, the transistor must be shortened in a lateral direction. However, reducing the channel length of the switching transistor 41 would involve various problems such as a drop in the threshold voltage and a decrease in the dielectric strength between the source region 37 and the drain region 38.
To avoid such problems, it would become necessary to reduce the supply voltage for the semiconductor memory device, which in turn would cause problems, for example, in terms of compatibility with other semiconductor memory devices.
There has also been proposed a semiconductor memory device having a vertical transistor and a trench capacitor as shown in FIG. 5 (see Morimoto et al., Japanese Laid-Open Patent Publication No. 61-224351). In this memory device, the trench capacitor is formed in a P-type silicon substrate 41 and the vertical transistor is formed on the substrate 41. The vertical transistor includes source/drain regions (N-type layers) 42 and 43 positioned one above the other with a channel region (P-type silicon epitaxial layer) 39 interposed therebetween, and also includes a gate electrode (N-type silicon layer) 44 functioning as a word line. A gate insulating layer 50 is interposed between the gate electrode 44 and the source, channel and drain regions (42, 39 and 43). The trench capacitor includes a charge storage layer 45 made of an N-type silicon layer, a capacitor-insulating film 51, and a plate electrode 40 made of a P-type silicon buried layer.
The channel region 39 is electrically in contact with the plate electrode 40 which is electrically in contact with the P-type silicon substrate 41. Accordingly, the channel region 39 of the switching transistor is electrically connected to the P-type silicon substrate 41 through the plate electrode 40 of the trench capacitor. In this arrangement, a substrate bias is applied to the switching transistor through the route shown by arrow A in FIG. 5, and a plate bias is applied to the memory cell through the route shown by arrow B in FIG. 5. Thus, this conventional memory device involves a problem in that a substrate bias and a plate bias cannot be separately applied to the switching transistor and the memory cell, respectively.